1. Field of the Invention
The present invention relates to a circuit for generating a pulse signal having a sequential low frequency portion and a high frequency portion having sharp pulse edges, particularly useful for input of a clock source input to a scan chain of a circuit under test for transition fault screening.
2. Background Information
In the production phase of integrated circuit development, transition fault testing is used to measure the time it takes for input data to propagate in the core of a circuit under test and to validate that time against defined propagation requirements. Even though circuit components may be connected adequately to propagate a signal at a slower speed and thus appear to operate correctly, they may propagate the signal too slowly at functional at-frequency clock speeds. In transition fault testing, the propagation delays between scan chains are stressed by reducing the time between a launch event and a capture event. Transition fault testing should exercise the circuit under test at functional at-frequency clock speeds in order for all flaws that will be present at such speeds to reveal themselves.
To properly test and measure the performance of a circuit undergoing transition fault testing, test input pulses must not only have the same data rate as functional clock speeds, but also must have a leading edge sharpness that will not impact the precise propagation of a test pulse, and its subsequent measurement. This is particularly important at the high data rates of present day integrated circuit computing devices, in which a pulse edge sharpness having a poor edge placement accuracy encompasses a functionally important portion of the entire pulse period. Recent advances in circuit design have provided integrated circuits that run at a clock speed that is great enough to make and require a pulse edge sharpness that traditional automatic test equipment do not generally provide. Speed failures in the core of these circuits under test should be run at the in-application functional clock speeds with in-application edge sharpness to properly test the circuits' propagation characteristics.
Contemporary integrated circuit testing configures a modification of at least some of the circuit under test sequential (or storage) elements to include a latch and a coupled switch, and the serial coupling of these sequential elements to form at least one shift register. Each serial coupling of the sequential elements is referred to as a scan chain. The test inputs from a test generator are scanned into the storage elements and the test results are scanned out of the storage elements through the scan chain elements. Each sequential element is additionally coupled to at least one combinational circuit element. Once a proper test input has been shifted into a scan element, it is switched to exercise the sequential-combinational circuit by transmitting the input pulse train to the circuit elements. The result is captured by the scan element, and when the scan element is switched into the scan chain shifting mode, transferred to a capturing circuit by the scan chain.
During a test of an integrated circuit, the pulse rate to load and unload a scan chain has to be slower than the transition fault pulse rate. This is because while a circuit is in normal operation, a relatively small number of transistors are operated at a time, but during a scan chain load and unload operation, a very large number of transistors are operated at a time, and if transition fault clocking speeds are used to load and unload the scan chain, the circuit will overheat and become damaged. The intra-scan chain propagation delays are not necessarily characterized to operate at functional speeds. In fact it would be quite difficult to arrange the circuitry and layout to optimize the propagation delays for both the functional and the scan pathways.
Thus, in order to transition fault test a circuit, the input waveform must switch from a low speed clock rate appropriate for scan chain loading and unloading, to suddenly and for just two or more pulses, a functional at-frequency clock rate which may be at least several hundred MHz and has a sharpened edge accuracy, and then back again to a slow clock rate.
The problem is that it is very difficult to generate a slow frequency pulse, switch for just a few pulses to a high frequency sharp edged pulse, and then back again to the slow pulse. What is needed is a circuit and method to utilize the conventional test equipment outputs that can only generate slow pulses sufficient in edge quality to load and unload a scan chain, and possibly somewhat faster pulses lacking the edge sharpness necessary to perform transition fault screening, to generate the waveform necessary for transition fault testing a scan chain, the waveform comprising slow frequency pulses and high frequency sharp edged pulses.